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GM72V66841ET/ELT
2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM
Description
The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock. The GM72V66841ET/ELT provides four banks of 2,097,152 word by 8 bit to realize high bandwidth with the Clock frequency up to 143 Mhz.
Pin Configuration
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BA0/A13 BA1/A12 A10,AP A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
JEDEC STANDARD 400 mil 54 PIN TSOP II (TOP VIEW)
Features
* PC133/PC100/PC66 Compatible -7(143MHz)/-75(133MHz)/-8(125MHz) -7K(PC100,2-2-2)/-7J(PC100,3-2-2) * 3.3V single Power supply * LVTTL interface * Max Clock frequency 143/133/125/100MHz * 4,096 refresh cycle per 64 ms * Two kinds of refresh operation Auto refresh / Self refresh * Programmable burst access capability ; - Sequence:Sequential / Interleave - Length :1/2/4/8/FP * Programmable CAS latency : 2/3 * 4 Banks can operate independently or simultaneously * Burst read/burst write or burst read/single write operation capability * Input and output masking by DQM input * One Clock of back to back read or write command interval * Synchronous Power down and Clock suspend capability with one Clock latency for both entry and exit * JEDEC Standard 54Pin 400mil TSOP II Package
VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
Pin Name
CLK CKE CS RAS CAS WE A0~A9,A11 A10 / AP BA0/A13 ~BA1/A12 DQ0~DQ7 DQM VCCQ VSSQ VCC VSS NC Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address input Address input or Auto Precharge Bank select Data input / Data output Data input / output Mask VCC for DQ VSS for DQ Power for internal circuit Ground for internal circuit No Connection
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any -1responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Apr.01
GM72V66841ET/ELT
Block Diagram
A0 to A13
A0 to A8
A0 to A13
Column address counter
Column address buffer
Row address counter
Refresh counter
Row decoder
Row decoder
Row decoder
Row decoder
Column decoder Sense amplifier & I/O bus
Column decoder Sense amplifier & I/O bus
Column decoder Sense amplifier & I/O bus
Memory array Bank 0 4096 row x 512 column x 8 bit
Memory array Bank 1 4096 row x 512 column x 8 bit
Memory array Bank 2 4096 row x 512 column x 8 bit
Column decoder Sense amplifier & I/O bus
Memory array Bank 3 4096 row x 512 column x 8 bit
Input buffer
Output buffer
Control logic & timing generator
RAS
CAS
WE
CKE
CLK
DQ0 to DQ7
DQM -2-
Rev. 1.1/Apr.01
CS
GM72V66841ET/ELT
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Notes : 1. Respect to VSS Symbol VT VCC IOUT PT Topr Tstg Value -0.5 to Vcc+0.5 (<= 4.6 (max)) -0.5 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1
Recommended DC Operating Conditions (Ta = 0 to + 70C)
Parameter Supply voltage VSS, VSSQ Input high voltage Input low voltage Notes : 1. All voltage referred to VSS. 2. VIH (max) = 5.6V for pulse width <= 3ns 3. VIL (min) = -2.0V for pulse width <= 3ns VIH VIL 0 2.0 -0.3 0 Vcc+0.3 0.8 V V V 1, 2 1,3 Symbol VCC, VCCQ Min 3.0 Max 3.6 Unit V Note 1
Rev. 1.1/Apr.01
-3-
GM72V66841ET/ELT DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V)
-7 Parameter Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down (CAS Latency=2) Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Symbol Max ICC1 ICC2P 85 Max 85 Max 80 2 2 ICC2PS 0.4 ICC2N 15 mA mA Max 80 Max 80 mA mA Burst length= 1 tRC = min CKE = VIL, tCK = 12 ns CKE=VIL, tCK= infinity CKE,CS = VIH, tCK = 12ns CKE = VIH, tCK = infinity CKE = VIL, tCK = 12 ns, DQ = High-Z CKE = VIL, tCK = infinity CKE,CS = VIH, tCK = 12 ns, DQ = High-Z CKE = VIH, tCK = infinity 1, 2, 3 5 6 6,8 4 - 75 -8 -7K -7J Unit Test conditions Notes
ICC2NS
12
mA
4
ICC3P
6
mA
1,2,5
ICC3PS
5
mA
2,6
ICC3N
30
mA
1,2,4
Active standby current in non power down ICC3NS (input signal stable) Burst operating current ( CL= 2 ) ( CL= 3 ) ICC4 ICC4 ICC5 ICC6 150 150
20
mA
2,9
120 150 160 1 120 120
mA mA mA mA
tCK = min
BL = 4
1,2,3
Refresh current
tRC = min
VIH >=VCC - 0.2 VIL <=0.2V
3 7 7,8
Self refresh current
0.4
Rev. 1.1/Apr.01
-4-
GM72V66841ET/ELT DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V) (Continued)
- 7, - 75, - 8, - 7K, - 7J Parameter Symbol Min Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL -1 -1.5 2.4 Max 1 1.5 0.4
uA
Unit Test conditions
Notes
0 <= Vin <=VCC 0<=Vout<=VCC DQ = disable
uA
V V
IOH = -2 mA IOL =2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC ( max) is specified at the output open condition. 2. One bank operation. 3. Addresses are changed once per one cycle. 4. Addresses are changed once per two cycles. 5. After Power down mode, CLK operating current. 6. After Power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. L-Version. 9. Input signals are VIH or VIL fixed.
Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V +/- 0.3 V)
Parameter Input capacitance (CLK) Input capacitance (Signals) Output capacitance (DQ) Symbol CI1 CI2 CO Min. 2.5 2.5 4.0 Max. 4 5 6.5 Unit pF pF pF Notes 1, 3, 4 1, 3, 4 1, 2, 3, 4
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. 4. Measured with 1.4 V bias and 200mV swing at the pin under measurement.
Rev. 1.1/Apr.01
-5-
GM72V66841ET/ELT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V)
-7 Parameter System clock cycle time (CL=2) (CL=3) Symbol Min Max Min Max Min Max Min Max Min Max - 75 -8 - 7K - 7J Unit Notes 10 7 2.5 2.5 2.7 1.5 1.5 0.8 1.5 0.8 1.5 1.5 0.8 1.5 6 5.4 5.4 10 7.5 2.5 2.5 2.7 1.5 1.5 0.8 1.5 0.8 1.5 1.5 0.8 1.5 6 5.4 5.4 10 8 3 3 3 2 2 1 2 1 2 2 1 2 6 6 6 10 10 3 3 3 2 2 1 2 1 2 2 1 2 6 6 6 15 10 3 3 3 2 2 1 2 1 2 2 1 2 ns 8 ns 6 6 ns ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1, 2 ns ns 1 1 1
CLK high pulse width CLK low pulse width Access time from CLK (CL=2) (CL=3)
Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance ( CL = 2,3 ) Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Command (CS, RAS, CAS, WE, DQM) setup time Command (CS, RAS, CAS, WE, DQM) hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period
tCK tCK tCKH tCKL tAC tAC tOH tLZ tHZ tDS tDH tAS tAH tCES tCESP tCEH tCS
tCH tRC tRAS tRCD tRP
0.8 62 42 20 20
120000
0.8 65 45 20 20
120000
1 68 48 20 20
120000
1 70 50 20 20
120000
1 70 50 20 20
120000
ns ns ns ns ns
1 1 1 1 1
-
-
-
-
-
Rev. 1.1/Apr.01
-6-
GM72V66841ET/ELT AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V) (Continued)
-7 Parameter Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Refresh period Symbol Min Max Min Max Min Max Min Max Min Max - 75 -8 - 7K - 7J Unit Notes 7 14 64 7.5 15 64 8 16 64 10 20 64 10 20 64 ns ns ms 1 1
tRWL tRRD tREF
Notes : 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V. If tT is longer than 1ns,transition time compensation should be considered. 2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination. 3. tLZ (min)defines the time at which the outputs achieves the low impedance state. 4. tHZ (max)defines the time at which the outputs achieves the high impedance state. 5. tCES define CKE setup time to CKE rising edge except Power down exit command.
Test Condition
* Input and output-timing reference levels: 1.4V * Input waveform and output load: See following figures I/O input 2.4V 0.4V 80% 20% CL OPEN
tT
tT
Rev. 1.1/Apr.01
-7-
GM72V66841ET/ELT
Relationship Between Frequency and Minimum Latency
Parameter frequency(MHz) Symbol -7 -75 -8 -7K -7J
66 15 2 6 4 2 1 2 2 3 6 2 3 1 -1 -2 1 0 0 2 1 1 0 1 143 100 133 100 125 100 100 100 100 7 10 2 7 5 2 1 2 1 3 7 2 3 1 -1 -2 1 0 0 2 1 1 0 1 7.5 3 9 6 3 1 2 1 4 9 3 1 -2 1 0 0 2 1 1 0 1 10 2 7 5 2 1 2 1 3 7 2 3 1 -1 -2 1 0 0 2 1 1 0 1 8 3 9 6 3 1 2 1 4 9 3 1 -2 1 0 0 2 1 1 0 1 10 2 7 5 2 1 2 2 3 7 2 3 1 -1 -2 1 0 0 2 1 1 0 1 10 2 7 5 2 1 2 1 3 7 2 3 1 -1 -2 1 0 0 2 1 1 0 1 10 2 7 5 2 1 2 1 3 7 2 3 1 -1 -2 1 0 0 2 1 1 0 1 10 2 7 5 2 1 2 1 3 7 3 1 -2 1 0 0 2 1 1 0 1
Notes
tCK (ns)
Active command to column command (same bank) Active command to active command (same bank) Active command to Precharge command (same bank) Precharge command to active command (same bank) Write recovery or last data-in to Precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto Precharge, same bank) Self refresh exit to command input Precharge (CL=2) command to (CL=3) high impedance Last data out to active command (auto Precharge) (same bank) Last data out to (CL=2) Precharge (CL=3) (early Precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command CS to command disable Power down exit to command input
lRCD lRC lRAS lRP lRWL lRRD lSREX lAPW lSEC lHZP lHZP lAPR lEP lEP lCCD lWCD lDID lDOD lCLE lRSA lCDD lPEC
3 9 6 3 1 2 1 4 9 3 1 -2 1 0 0 2 1 1 0 1
1 = [lRAS +lRP], 1 1 1 1 1
= [lRWL +lRP], 1 = [lRC]
Rev. 1.1/Apr.01
-8-
GM72V66841ET/ELT
Relationship Between Frequency and Minimum Latency
Parameter frequency(MHz) -7 -75 -8 - 7K - 7J
66 15 1 2 2 3 0
Symbol 143 100 133 100 125 100 100 100 100
7 10 1 2 2 3 0 7.5 2 3 0 10 1 2 2 3 0 8 2 3 0 10 1 2 2 3 0 10 1 2 2 3 0 10 1 2 2 3 0 10 2 3 0
Notes
tCK (ns)
Burst stop to output valid data hold Burst stop to output high impedance (CL=2) (CL=3) (CL=2) (CL=3)
Burst stop to write data ignore
lBSR lBSR lBSH lBSH lBSW
2 3 0
Notes : 1. lRCD to lRRD are recommended value.
Rev. 1.1/Apr.01
-9-
GM72V66841ET/ELT
Package Dimensions
GM72V66841ET/ELT Series (TTP-54D)
Preliminary
22.22 54 22.72 Max 28
Unit: (mm)
1 0.30 0.28 +/- 0.05
+0.10 - 0.05
0.80 0.13 M
27
10.16
0.80 0.91 MAX 11.76 +/- 0.20
0 ~ 5
1.20 MAX
0.125 +/- 0.04
0.145 +/- 0.05
0.13 +/- 0.05
0.10
0.50 +/- 0.10
Hitachi Code JEDEC Code
TTP-54D 0.53g
Dimension including the plating thickness Base material dimension
EIAJ Code Weight(reference value)
0.68
Rev. 1.1/Apr.01
-10-

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